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arXiv cs.CL·

ESBMC-PLC: Formal Verification of IEC 61131-3 Ladder Diagram Programs Using SMT-Based Model Checking

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In three linesESBMC-PLC is the first open-source formal verifier with native support for IEC 61131-3 ladder diagrams (PLCopen XML format). The tool translates rungs to GOTO IR, models the PLC scan cycle, and verifies safety properties via SMT-based bounded model checking or k-induction. Evaluation on 13 benchmarks: 8 bugs detected, 7 unbounded k-induction proofs, all runs under 60ms.
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