TinyTPU: SystemVerilog systolic array compiled to WASM, running live in browser - RTL golden-verified against numpy [P]

In three linesTinyTPU is a 4×4 weight-stationary systolic array in SystemVerilog compiled to WebAssembly with step-by-step browser visualization. Users enter two matrices and watch actual hardware execution: weights loading into processing elements, matrix A streaming diagonally, partial sums accumulating, results draining. Three levels: single MAC cell, full 4×4 array matmul, and tiling for larger matrices.

Summary generated by Claude — human-verified