Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation

In three linesVerilog-Evolve is a feedback-driven framework for iterative Verilog refinement from LLM generation. The system evaluates candidates via functional simulation, Yosys synthesis, ABC timing proxy, and GEMM metrics, then evolves modular skills across tasks. Results on VerilogEval show improved functional success and downstream RTL quality.

Summary generated by Claude — human-verified